The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulating layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner. The various layers define circuit components or devices such as transistors.
After the individual devices have been fabricated on the substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally known as “metallization” and is performed using a number of different photolithographic, deposition, and removal techniques. In a common interconnection process, two interconnect channels of conductor materials are separated by interlayer dielectric layers in vertically separated planes perpendicular to each other and interconnected by a vertical connection, or “via”, at their closest point.
A conventional device structure 65 is shown in FIG. 1. In fabrication of the device structure 65, via openings 74 are typically formed by initial deposition of a silicon dioxide intermetal dielectric (IMD) layer 68 of desired thickness which corresponds to the thickness for the via openings 74 to be etched in the IMD layer 68. The IMD layer 68 covers metal lines 67 fabricated in or on a wafer 66. Photolithography and dry etching are used to pattern and etch the via openings 74 in the IMD layer 68.
Next, a barrier layer 70 of Ta or TaN is deposited on the sidewalls and bottoms of the via openings 74. A uniform copper seed layer 71 is then deposited on the barrier layer 74 using CVD. After the trenches and vias are filled with a copper via plug 69 in a single copper inlay step, the copper overburden extending from the via openings 74 is removed and the upper surfaces of the metal lines planarized using CMP. An additional metal line 73 is formed on the IMD layer 68, in electrical contact with each via plug 69.
After formation of the via plugs 69, the device structure 65 is typically subjected to a thermal anneal step which is carried out in an RTP (rapid thermal processing) chamber (not shown). As shown in FIG. 2, in the RTP chamber the wafer 66 is placed on a wafer heater 75, with the heating surface of the wafer heater 75 disposed in direct physical and thermal contact with the backside of the wafer 66. The anneal step reduces the electrical resistance of the via plugs 69 in the device structure 65.
In the thermal anneal step, the wafer 66 is directly heated by the wafer heater 75. After initial placement of the wafer 66 on the wafer heater 75, the wafer heater 75 is gradually heated to a target temperature. Frequently, however, the actual processing temperature overshoots the target temperature for the wafer 66. Furthermore, the presence of particles (not shown) which remain on the wafer heater 75 upon placement of the wafer 66 thereon adversely affect the heating performance of the wafer heater 75. Moreover, the wafer-heating characteristics vary among different RTP chambers in a processing sequence, resulting in different results among multiple wafers in a lot or between lots.
As further shown in FIG. 1, voids 72 are a common structural anomaly which occurs in the via plug 69 as a result of imprecise or unstable heating of the wafer 66 during the thermal anneal process. These voids 72 partially or completely break electrical communication between the lower-level metal lines 67 and upper-level metal lines 73 in the device structure 65. Accordingly, a method is needed for preventing the formation of voids in via plugs, particularly during a thermal anneal process carried out to reduce the electrical resistance of the via plugs in a device structure.
An object of the present invention is to provide a novel method for preventing the formation of voids in via plugs.
Another object of the present invention is to provide a novel method for preventing the formation of voids in via plugs by providing uniform and stable heating of a wafer during a thermal anneal process.
Still another object of the present invention is to provide a novel void formation prevention method in which uniform and stable heating of a wafer during a thermal anneal process is carried out by providing a wafer heater and spacing the wafer from the wafer heater.
Yet another object of the present invention is to provide a novel void formation prevention method in which a wafer is spaced from a wafer heater to facilitate uniform and stable heating of the wafer during a thermal anneal process by providing multiple spacer pins on the wafer heater and supporting the wafer on the spacer pins, above the heater during the thermal anneal process.
A still further object of the present invention is to provide a novel void formation prevention method in which a wafer is spaced from a wafer heater to facilitate uniform and stable heating of the wafer during a thermal anneal process by providing at least one gripper block, causing engagement of the gripper block with the wafer and supporting the wafer above the wafer heater during the thermal anneal process.